This application relates generally to processor-based systems, and, more particularly, to throttling data cache prefetching in processor-based systems.
Many processing devices utilize caches to reduce the average time required to access information stored in a memory. A cache is a smaller and faster memory that stores copies of instructions or data that are expected to be used relatively frequently. For example, central processing units (CPUs), but one type of processor that uses caches, are generally associated with a cache or a hierarchy of cache memory elements. Other processors, such as graphics processing units, can also implement cache systems. Instructions or data that are expected to be used by the CPU are moved from (relatively large and slow) main memory into the cache. When the CPU needs to read or write a location in the main memory, it first checks to see whether a copy of the desired memory location is included in the cache memory. If this location is included in the cache (a cache hit), then the CPU can perform the read or write operation on the copy in the cache memory location. If this location is not included in the cache (a cache miss), then the CPU needs to access the information stored in the main memory and, in some cases, the information can be copied from the main memory and added to the cache. Proper configuration and operation of the cache can reduce the average latency of memory accesses to a value below the main memory latency and close to the cache access latency.
A prefetcher can be used to populate the lines in the cache before the information in these lines has been requested. The prefetcher can monitor memory requests associated with applications running in the processor and use the monitored requests to determine or predict that the processor (e.g., a CPU) is likely to access a particular sequence of memory addresses in the main memory. For example, the prefetcher may detect sequential memory accesses by the CPU by monitoring a miss address buffer that stores addresses of previous cache misses. The prefetcher then fetches the information from locations in the main memory in a sequence (and direction) determined by the sequential memory accesses in the miss address buffer and stores this information in the cache so that the information is available before it is requested by the CPU. Prefetchers can keep track of multiple streams and independently prefetch data for the different streams.